Fpga Single Event Effect Mitigation With Smart Redundancy
ID U-7194
Category Hardware, Circuits, & Sensors
Subcategory Semiconductors
Researchers
Brief Summary
Smart-Redundancy Field Programmable Gate Arrays (FPGAs)
Problem Statement
FPGAs configuration memories exposition to ionizing particle threaten the component behavior. State-of-the-art Radiation-Hardening (Rad-Hard) methods for FPGAs consist of triplicating the logic, reinforcing the memories, and bitstream scrubbing with partial reconfiguration. These methods involve a 3x reduction of Maximal Design Capacity (MDC) and an average Time-In-Error (TIE) proportional to design sizes.
Technology Description
Researchers at the University of Utah have developed an innovation that solves the problem Single Event Effects on electronics devices. Smart-Redundancy (SR), a new method based on the detection of possible events via process and hardware modifications. With integrated particle sensors, only dual redundancy is required. The invention protects the component via a sensor integration to instantaneously detect errors. Based on the error detection the faulty values are repaired. The innovation features True Dual Redundancy and while an element is repaired the redundant element guarantee the expected behavior. It drastically reduces memory time in error and reduces the required number of logic element and the routing complexity.
Stage of Development
Concept
Benefit
- Up to 33.33% improvement in MDC over actual Rad-Hard methods
- An average TIE decrease of at least 10,000x compared to bitstream’s scrubbing
- A reduced cost of 41.08% in area using a commercial 40nm technology node
IP
Publication Number: US 2023-0170038 A1
Patent Title: Single Event Effect Mitigation with Smart-Redundancy
Jurisdiction/Country: United States
Application Type: Non-Provisional
Contact Info
Dean Gallagher
(801) 585-0396
dean.gallagher@utah.edu